Reconfigurable FPGA designs enable extremely flexible and powerful parallel processing architecture, yet have been somewhat impeded by a lack of evaluation tools. The complexity of today's design makes it almost impossible to debug a design using traditional logic analysis methods. Evaluation often captures over 50% of the development time. Thus, an efficient flexible evaluation tool that is founded on accurate signal capture and abundant visibility depth is essential to accelerating/optimizing the developmental cycle. Another approach for evaluation is Emulation, but it is much slower and much more expensive.